The Complete Verilog Book

• Κύριος συγγραφέας: Sagdeo, Vivek (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 1998.
• Θέματα: Engineering.; Computer hardware.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Computer Hardware.; Computer-Aided Engineering (CAD, CAE) and Design.; Electrical Engineering.

The Verilog hardware description language (HDL) provides the ability to describe digital and analog systems. This ability spans the range from descriptions that express conceptual and architectural design to detailed descriptions of implementations in gates and transistors. Verilog was developed ori...

Πίνακας περιεχομένων:

• to Verilog HDL
• Data Types in Verilog
• Abstraction Levels in Verilog: Behavioral, RTL, and Structural
• Semantic Model for Verilog HDL
• Behavioral Modeling
• Structural Primitive Modeling
• Mixed Structural, RTL, and Behavioral Design
• System Tasks and Functions
• Compiler Directives
• Interactive Simulation and Debugging
• System Examples
• Synthesis with Verilog
• Verilog Subset for Logic Synthesis
• Special Considerations in Synthesizing Verilog
• Specify Blocks — Timing Descriptions
• Programming Language Interface
• Strength Modeling with Transistors
• Standard Delay Format
• Verilog-A and Verilog-MS
• Simulation Speedup Techniques
• Formal Syntax Definition for Verilog HDL
• Verilog Subset for Logic Synthesis
• Programming Language Interface (PLI) Header File — veriuser.h
• Programming Language Interface (PLI) header File — acc _user.h
• Programming Language Interface (PLI) Header File — vpi_user.h file
• Formal Syntax Definition of SDF.