Writing Testbenches Functional Verification of HDL Models /

Writing Testbenches Functional Verification of HDL Models /

CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας:	Bergeron, Janick (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή:	SpringerLink (Online service)
Μορφή:	Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:	English
Έκδοση:	Boston, MA : Springer US, 2000.
Θέματα:	Engineering. Computer hardware. Computer-aided engineering. Electrical engineering. Electronic circuits. Circuits and Systems. Computer Hardware. Electrical Engineering. Computer-Aided Engineering (CAD, CAE) and Design.
Διαθέσιμο Online:	Full Text via HEAL-Link

Παρόμοια τεκμήρια

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System Design with SystemC
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The Complete Verilog Book
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The Designer’s Guide to Verilog-AMS, June 2004
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High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test
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System-on-a-Chip Verification Methodology and Techniques /
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Design, Simulation and Applications of Inductors and Transformers for Si RF ICs
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