Writing Testbenches Functional Verification of HDL Models /

• Main Author: Bergeron, Janick (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2000.
• Subjects: Engineering.; Computer hardware.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Computer Hardware.; Electrical Engineering.; Computer-Aided Engineering (CAD, CAE) and Design.

CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness...

Table of Contents:

• What is Verification?
• Verification Tools
• The Verification Plan
• Behavioral Hardware Description Languages
• Stimulus and Response
• Architecting Testbenches
• Simulation Management.