High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test
Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and te...
Main Author: | Adams, R. Dean (Author) |
---|---|
Corporate Author: | SpringerLink (Online service) |
Format: | Electronic eBook |
Language: | English |
Published: |
Boston, MA :
Springer US,
2003.
|
Series: | Frontiers in Electronic Testing,
22A |
Subjects: | |
Online Access: | Full Text via HEAL-Link |
Similar Items
-
A Designer’s Guide to Built-In Self-Test
by: Stroud, Charles E.
Published: (2002) -
CTL for Test Information of Digital ICS
by: Kapur, Rohit
Published: (2002) -
Power-constrained Testing of VLSI Circuits
by: Nicolici, Nicola, et al.
Published: (2003) -
Nanometer Technology Designs High-Quality Delay Tests
by: Tehranipoor, Mohammad, et al.
Published: (2008) -
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
by: Bushnell, Michael L., et al.
Published: (2002)