Low-Voltage CMOS Log Companding Analog Design

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSF...

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Bibliographic Details
Main Authors: Serra-Graells, Francisco (Author), Rueda, Adoración (Author), Huertas, José L. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Boston, MA : Springer US, 2003.
Series:The International Series in Engineering and Computer Science, Analog Circuits and Signal Processing, 733
Subjects:
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ΒΚΠ - Πατρα: ALFd

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Call Number: 330.01 BAU
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ΒΚΠ - Πατρα: BSC

Holdings details from ΒΚΠ - Πατρα: BSC
Call Number: 330.01 BAU
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