Networks on Chip
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. T...
Συγγραφή απο Οργανισμό/Αρχή: | |
---|---|
Άλλοι συγγραφείς: | , |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2003.
|
Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- System Design and Methodology
- Will Networks on Chip Close the Productivity Gap?
- A Design Methodology for NOC-Based Systems
- Mapping Concurrent Applications onto Architectural Platforms
- Guaranteeing the Quality of Services in Networks on Chip
- Hardware and Basic Infrastructure
- On Packet Switched Networks for On-Chip Communication
- Energy-Reliability trade-Off for NoCs
- Testing Strategies for Networks on Chip
- Clocking Strategies for Networks-on-Chip
- A Parallel Computer as a NOC Region
- An IP-Based On-Chip Packet-Switched Network
- Software and Application Interfaces
- Beyond the Von Neumann Machine
- NoC Application Programming Interfaces
- Multi-Level Software Validation for NoC
- Software for Multiprocessor Networks on Chip.