Verification by Error Modeling Using Testing Techniques in Hardware Verification /

• Κύριοι συγγραφείς: Radecka, Katarzyna (Συγγραφέας), Zilic, Zeljko (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 2003.
• Σειρά: Frontiers in Electronic Testing, 25
• Θέματα: Engineering.; Computers.; Computer-aided engineering.; Robotics.; Automation.; Electrical engineering.; Electronic circuits.; Robotics and Automation.; Circuits and Systems.; Electrical Engineering.; Computer-Aided Engineering (CAD, CAE) and Design.; Computing Methodologies.

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, incl...

Πίνακας περιεχομένων:

• Boolean Function Representations
• Don’t Cares and Their Calculation
• Testing
• Design Error Models
• Design Verification by At
• Identifying Redundant Gate and Wire Replacements
• Conclusions and Future Work.