Taxonomies for the Development and Verification of Digital Systems
"In the complicated world of system-on-chip design, we need a common language so we know what we're talking about. By providing definitions for the terms used in the modeling, implementation, and verification of electronic systems, the taxonomies described in this book will help us find a...
| Corporate Author: | SpringerLink (Online service) |
|---|---|
| Other Authors: | Bailey, Brian (Editor), Martin, Grant (Editor), Anderson, Thomas (Editor) |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2005.
|
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
Similar Items
-
A Roadmap for Formal Property Verification
by: DasGupta, Pallab
Published: (2006) -
Standardized Functional Verification
by: Wiemann, Alan
Published: (2008) -
VLSI Physical Design: From Graph Partitioning to Timing Closure
by: Kahng, Andrew B., et al.
Published: (2011) -
System Verilog for Verification A Guide to Learning the Testbench Language Features /
by: Spear, Chris
Published: (2008) -
Taxonomies for the Development and Verification of Digital Systems
by: Bailey, Brian
Published: (2005)