Verification Methodology Manual for SystemVerilog
Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that thes...
| Main Authors: | Bergeron, Janick (Author), Cerny, Eduard (Author), Hunter, Alan (Author), Nightingale, Andrew (Author) |
|---|---|
| Corporate Author: | SpringerLink (Online service) |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2006.
|
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
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