Scalable Hardware Verification with Symbolic Simulation
Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner working...
| Main Author: | Bertacco, Valeria (Author) |
|---|---|
| Corporate Author: | SpringerLink (Online service) |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2006.
|
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
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