SystemVerilog for Design A Guide to Using SystemVerilog for Hardware Design and Modeling /

• Κύριοι συγγραφείς: Sutherland, Stuart (Συγγραφέας), Davidmann, Simon (Συγγραφέας), Flake, Peter (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 2006.
• Έκδοση: Second Edition.
• Θέματα: Engineering.; Computer hardware.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.; Computer Hardware.; Electrical Engineering.

SystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs. These important extensions enable the representation of complex digital logic in concise, accur...

Πίνακας περιεχομένων:

• to SystemVerilog
• SystemVerilog Declaration Spaces
• SystemVerilog Literal Values and Built-in Data Types
• SystemVerilog User-Defined and Enumerated Types
• SystemVerilog Arrays, Structures and Unions
• SystemVerilog Procedural Blocks, Tasks and Functions
• SystemVerilog Procedural Statements
• Modeling Finite State Machines with SystemVerilog
• SystemVerilog Design Hierarchy
• SystemVerilog Interfaces
• A Complete Design Modeled with SystemVerilog
• Behavioral and Transaction Level Modeling.