APA (7th ed.) Citation

Jespers, P. (2010). The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits: The semi-empirical and compact model approaches. Springer US.

Chicago Style (17th ed.) Citation

Jespers, Paul. The G M /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches. Boston, MA: Springer US, 2010.

MLA (8th ed.) Citation

Jespers, Paul. The G M /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits: The Semi-empirical and Compact Model Approaches. Springer US, 2010.