Saxena, P., Shelar, R. S., & Sapatnekar, S. S. (2007). Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer US.
Chicago Style (17th ed.) CitationSaxena, Prashant, Rupesh S. Shelar, and Sachin S. Sapatnekar. Routing Congestion in VLSI Circuits: Estimation and Optimization. Boston, MA: Springer US, 2007.
MLA (8th ed.) CitationSaxena, Prashant, et al. Routing Congestion in VLSI Circuits: Estimation and Optimization. Springer US, 2007.
Warning: These citations may not always be 100% accurate.