Routing Congestion in VLSI Circuits: Estimation and Optimization

• Κύριοι συγγραφείς: Saxena, Prashant (Συγγραφέας), Shelar, Rupesh S. (Συγγραφέας), Sapatnekar, Sachin S. (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 2007.
• Σειρά: Series on Integrated Circuits and Systems,
• Θέματα: Engineering.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.; Communications Engineering, Networks.

With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intel...