SAT-Based Scalable Formal Verification Solutions

• Main Authors: Ganai, Malay K. (Author), Gupta, Aarti (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2007.
• Series: Series on Integrated Circuits and Systems,
• Subjects: Computer science.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Computer Science.; Computer-Aided Engineering (CAD, CAE) and Design.; Circuits and Systems.; Electrical Engineering.

Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and int...

Table of Contents:

• Design Verification Challenges
• Design Verification Challenges
• Background
• Basic Infrastructure
• Efficient Boolean Representation
• Hybrid DPLL-Style SAT Solver
• Falsification
• SAT-Based Bounded Model Checking
• Distributed SAT-Based BMC
• Efficient Memory Modeling in BMC
• BMC for Multi-Clock Systems
• Proof Methods
• Proof by Induction
• Unbounded Model Checking
• Abstraction/Refinement
• Proof-Based Iterative Abstraction
• Verification Procedure
• SAT-Based Verification Framework
• Synthesis for Verification.