Low Power Methodology Manual For System-on-Chip Design /
"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to...
| Main Authors: | , , , , |
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| Corporate Author: | |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2007.
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| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
Table of Contents:
- Standard Low Power Methods
- Multi-Voltage Design
- Power Gating Overview
- Designing Power Gating
- Architectural Issues for Power Gating
- A Power Gating Example
- IP Design for Low Power
- Frequency and Voltage Scaling Design
- Examples of Voltage and Frequency Scaling Design
- Implementing Multi-Voltage, Power Gated Designs
- Physical Libraries
- Retention Register Design
- Design of the Power Switching Network.