Nanometer Technology Designs High-Quality Delay Tests
While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip...
| Main Authors: | Tehranipoor, Mohammad (Author), Ahmed, Nisar (Author) |
|---|---|
| Corporate Author: | SpringerLink (Online service) |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2008.
|
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
Similar Items
-
Leakage in Nanometer CMOS Technologies
by: Narendra, Siva G., et al.
Published: (2006) -
The Core Test Wrapper Handbook Rationale and Application of IEEE Std. 1500™ /
by: Silva, Francisco da, et al.
Published: (2006) -
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
by: Bushnell, Michael L., et al.
Published: (2002) -
Ultra Low-Power Electronics and Design
Published: (2004) -
Substrate Noise Coupling in Mixed-Signal ASICs
Published: (2003)