Nanometer Technology Designs High-Quality Delay Tests

• Main Authors: Tehranipoor, Mohammad (Author), Ahmed, Nisar (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2008.
• Subjects: Engineering.; Computer-aided engineering.; Electrical engineering.; Electronics.; Microelectronics.; Electronic circuits.; Nanotechnology.; Circuits and Systems.; Electronics and Microelectronics, Instrumentation.; Computer-Aided Engineering (CAD, CAE) and Design.; Electrical Engineering.

While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip...

Table of Contents:

• Introduction to path delay and transition delay fault models and test methods
• At-speed test challenges for nanometer technology designs
• Low-cost tester friendly design-for-test techniques
• Improving test quality of current at-speed test methods
• Functionally untestable fault list generation and avoidance
• Timing-based ATPG for screening small delay faults
• Faster-than-at-speed test considering IR-drop effects
• IR-drop tolerant at-speed test pattern generation and application.