Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) r...
Κύριοι συγγραφείς: | , , , |
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Συγγραφή απο Οργανισμό/Αρχή: | |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2008.
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- High-Level Synthesis Fundamentals
- Power Modeling and Estimation at Transistor and Logic Gate Levels
- Architectural Power Modeling and Estimation
- Power Reduction Fundamentals
- Energy or Average Power Reduction
- Peak Power Reduction
- Transient Power Reduction
- Leakage Power Reduction
- Conclusions and Future Direction.