Full-Chip Nanometer Routing Techniques

Full-Chip Nanometer Routing Techniques

As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς:	Ho, Tsung-Yi (Συγγραφέας), Chang, Yao-Wen (Συγγραφέας), Chen, Sao-Jie (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή:	SpringerLink (Online service)
Μορφή:	Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:	English
Έκδοση:	Dordrecht : Springer Netherlands, 2007.
Σειρά:	Analog Circuits And Signal Processing Series
Θέματα:	Engineering. Computer-aided engineering. Electronic circuits. Nanotechnology. Circuits and Systems. Computer-Aided Engineering (CAD, CAE) and Design.
Διαθέσιμο Online:	Full Text via HEAL-Link

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Advanced Test Methods for SRAMs Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies /
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Designing Embedded Systems with the SIGNAL Programming Language Synchronous, Reactive Specification /
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Minimizing and Exploiting Leakage in VLSI Design
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Integrated Optical Interconnect Architectures for Embedded Systems
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Power-efficient System Design
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