Full-Chip Nanometer Routing Techniques

• Κύριοι συγγραφείς: Ho, Tsung-Yi (Συγγραφέας), Chang, Yao-Wen (Συγγραφέας), Chen, Sao-Jie (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Dordrecht : Springer Netherlands, 2007.
• Σειρά: Analog Circuits And Signal Processing Series
• Θέματα: Engineering.; Computer-aided engineering.; Electronic circuits.; Nanotechnology.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.

As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...

Πίνακας περιεχομένων:

• Routing Challenges for Nanometer Technology
• Multilevel Full-Chip Routing Considering Crosstalk And Performance
• Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
• Multilevel Full-Chip Routing For The X-Based Architecture
• Concluding Remarks And Future Work.