Full-Chip Nanometer Routing Techniques

As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...

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Bibliographic Details
Main Authors: Ho, Tsung-Yi (Author), Chang, Yao-Wen (Author), Chen, Sao-Jie (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Dordrecht : Springer Netherlands, 2007.
Series:Analog Circuits And Signal Processing Series
Subjects:
Online Access:Full Text via HEAL-Link

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