Direct Transistor-level Layout for Digital Blocks
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout...
| Main Authors: | , |
|---|---|
| Corporate Author: | |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2005.
|
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
Internet
Full Text via HEAL-LinkΒΚΠ - Πατρα: ALFd
| Call Number: |
330.01 BAU |
|---|---|
| Copy 1 | Available |
ΒΚΠ - Πατρα: BSC
| Call Number: |
330.01 BAU |
|---|---|
| Copy 2 | Available |
| Copy 3 | Available |