Direct Transistor-level Layout for Digital Blocks

• Main Authors: Gopalakrishnan, Prakash (Author), Rutenbar, Rob A. (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2005.
• Subjects: Engineering.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Electrical Engineering.; Computer-Aided Engineering (CAD, CAE) and Design.

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout...

Table of Contents:

• Circuit Structure and Clustering
• Global Placement
• Detailed Placement and Layout Results
• Timing-Driven Placement
• Conclusion.