Direct Transistor-level Layout for Digital Blocks

• Κύριοι συγγραφείς: Gopalakrishnan, Prakash (Συγγραφέας), Rutenbar, Rob A. (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US, 2005.
• Θέματα: Engineering.; Computer-aided engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Electrical Engineering.; Computer-Aided Engineering (CAD, CAE) and Design.

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout...

Πίνακας περιεχομένων:

• Circuit Structure and Clustering
• Global Placement
• Detailed Placement and Layout Results
• Timing-Driven Placement
• Conclusion.