Direct Transistor-level Layout for Digital Blocks

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout...

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Bibliographic Details
Main Authors: Gopalakrishnan, Prakash (Author), Rutenbar, Rob A. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Boston, MA : Springer US, 2005.
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ΒΚΠ - Πατρα: ALFd

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Call Number: 330.01 BAU
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Call Number: 330.01 BAU
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