CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς:	Pavlov, Andrei (Συγγραφέας), Sachdev, Manoj (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή:	SpringerLink (Online service)
Μορφή:	Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:	English
Έκδοση:	Dordrecht : Springer Netherlands, 2008.
Σειρά:	Frontiers In Electronic Testing, 40
Θέματα:	Engineering. Computer memory systems. Electronic circuits. Circuits and Systems. Memory Structures.
Διαθέσιμο Online:	Full Text via HEAL-Link

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