CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...

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Bibliographic Details
Main Authors: Pavlov, Andrei (Author), Sachdev, Manoj (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Dordrecht : Springer Netherlands, 2008.
Series:Frontiers In Electronic Testing, 40
Subjects:
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ΒΚΠ - Πατρα: ALFd

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Call Number: 330.01 BAU
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ΒΚΠ - Πατρα: BSC

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Call Number: 330.01 BAU
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