CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...
Main Authors: | , |
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Corporate Author: | |
Format: | Electronic eBook |
Language: | English |
Published: |
Dordrecht :
Springer Netherlands,
2008.
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Series: | Frontiers In Electronic Testing,
40 |
Subjects: | |
Online Access: | Full Text via HEAL-Link |
Internet
Full Text via HEAL-LinkΒΚΠ - Πατρα: ALFd
Call Number: |
330.01 BAU |
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Copy 1 | Available |
ΒΚΠ - Πατρα: BSC
Call Number: |
330.01 BAU |
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Copy 2 | Available |
Copy 3 | Available |