Low-Power High-Speed ADCs for Nanometer CMOS Integration

• Main Authors: Cao, Zhiheng (Author), Yan, Shouli (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Dordrecht : Springer Netherlands, 2008.
• Series: Analog Circuits and Signal Processing Series
• Subjects: Engineering.; Energy.; Electric power production.; Electronic circuits.; Circuits and Systems.; Energy Technology.; Energy, general.

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique...

Table of Contents:

• A 52 mW 10 b 210 MS/s Two-Step ADC for Digital IF Receivers in 130 nm CMOS
• A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 130 nm Digital CMOS
• A 0.4 ps-RMS-Jitter 1–3 GHz Clock Multiplier PLL Using Phase-Noise Preamplification
• Conclusions and Future Directions.