Generating Hardware Assertion Checkers For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /

• Κύριοι συγγραφείς: Boulé, Marc (Συγγραφέας), Zilic, Zeljko (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Dordrecht : Springer Netherlands, 2008.
• Θέματα: Engineering.; Programming languages (Electronic computers).; Computers.; Electronic circuits.; Circuits and Systems.; Theory of Computation.; Programming Languages, Compilers, Interpreters.

 Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. The PSL and SVA languages are treated in a unified way, thereby facilitating better learning and usage of the modern assertion languages, with a focus on obtaining the highest performance from assertion checkers. The obtained checkers are thoroughly benchmarked and verified, while formal proofs using automated reasoning techniques are explained. Included are examples of practical circuits (PCI, AMBA, Wishbone-PIC, CPU Pipeline) and their assertion checker synthesis. 

 Assertions and the Verification Landscape -- Basic Techniques Behind Assertion Checkers -- PSL and SVA Assertion Languages -- Automata for Assertion Checkers -- Construction of PSL Assertion Checkers -- Enhanced Features and Uses of PSL Checkers -- Evaluating and Verifying PSL Assertion Checkers -- Checkers for SystemVerilog Assertions -- Conclusions and Future Work.