Planar Double-Gate Transistor From Technology to Circuit /

This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and c...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Άλλοι συγγραφείς: Amara, Amara (Επιμελητής έκδοσης), Rozeau, Olivier (Επιμελητής έκδοσης)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Dordrecht : Springer Netherlands, 2009.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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245 1 0 |a Planar Double-Gate Transistor  |h [electronic resource] :  |b From Technology to Circuit /  |c edited by Amara Amara, Olivier Rozeau. 
264 1 |a Dordrecht :  |b Springer Netherlands,  |c 2009. 
300 |a VIII, 211 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design. 
520 |a This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates. 
650 0 |a Engineering. 
650 0 |a Solid state physics. 
650 0 |a Spectroscopy. 
650 0 |a Microscopy. 
650 0 |a Electronic circuits. 
650 0 |a Optical materials. 
650 0 |a Electronic materials. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Solid State Physics. 
650 2 4 |a Spectroscopy and Microscopy. 
650 2 4 |a Optical and Electronic Materials. 
700 1 |a Amara, Amara.  |e editor. 
700 1 |a Rozeau, Olivier.  |e editor. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781402093272 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4020-9341-8  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)