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03647nam a22005055i 4500 |
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978-1-4020-9365-4 |
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|a 9781402093654
|9 978-1-4020-9365-4
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|a 10.1007/978-1-4020-9365-4
|2 doi
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|a TK7888.4
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|a TEC008010
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|a 621.3815
|2 23
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|a Chang, Kai-hui.
|e author.
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|a Functional Design Errors in Digital Circuits
|h [electronic resource] :
|b Diagnosis, Correction and Repair /
|c by Kai-hui Chang, Igor L. Markov, Valeria Bertacco.
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|a Dordrecht :
|b Springer Netherlands,
|c 2009.
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|a XXIV, 200 p.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
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|a online resource
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|a text file
|b PDF
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|a Lecture Notes in Electrical Engineering,
|x 1876-1100 ;
|v 32
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|a Background and Prior Art -- Current Landscape in Design and Verification -- Finding Bugs and Repairing Circuits -- FogClear Methodologies and Theoretical Advances in Error Repair -- Circuit Design and Verification Methodologies -- Counterexample-Guided Error-Repair Framework -- Signature-Based Resynthesis Techniques -- Symmetry-Based Rewiring -- FogClear Components -- Bug Trace Minimization -- Functional Error Diagnosis and Correction -- Incremental Verification for Physical Synthesis -- Post-Silicon Debugging and Layout Repair -- Methodologies for Spare-Cell Insertion -- Conclusions.
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|a Due to the dramatic increase in design complexity, modern circuits are often produced with functional errors. While improvements in verification allow engineers to find more errors, fixing these errors remains a manual and challenging task. Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. In addition, Functional Design Errors in Digital Circuits Diagnosis describes a comprehensive evaluation of spare-cell insertion methods. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.
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|a Engineering.
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|a Logic design.
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|a Computer-aided engineering.
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|a Electronic circuits.
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|a Engineering.
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|a Circuits and Systems.
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|a Computer-Aided Engineering (CAD, CAE) and Design.
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|a Logic Design.
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|a Markov, Igor L.
|e author.
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|a Bertacco, Valeria.
|e author.
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2 |
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|a SpringerLink (Online service)
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|t Springer eBooks
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|i Printed edition:
|z 9781402093647
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830 |
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|a Lecture Notes in Electrical Engineering,
|x 1876-1100 ;
|v 32
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856 |
4 |
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|u http://dx.doi.org/10.1007/978-1-4020-9365-4
|z Full Text via HEAL-Link
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912 |
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|a ZDB-2-ENG
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|a Engineering (Springer-11647)
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