Offset Reduction Techniques in Highspeed Analog-To-Digital Converters Analysis, Design and Tradeoffs /

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitatio...

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Bibliographic Details
Main Authors: Figueiredo, Pedro M. (Author), Vital, JoÃo C. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Dordrecht : Springer Netherlands, 2009.
Series:Analog Circuits and Signal Processing Series
Subjects:
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ΒΚΠ - Πατρα: ALFd

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Call Number: 330.01 BAU
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ΒΚΠ - Πατρα: BSC

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Call Number: 330.01 BAU
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