Designing Reliable and Efficient Networks on Chips

• Κύριος συγγραφέας: Murali, Srinivasan (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Dordrecht : Springer Netherlands, 2009.
• Σειρά: Lecture Notes in Electrical Engineering, 34
• Θέματα: Engineering.; Microprocessors.; Electronic circuits.; Power electronics.; Circuits and Systems.; Power Electronics, Electrical Machines and Networks.; Processor Architectures.

 Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design. 

 NoC Design Methods -- Designing Crossbar Based Systems -- Netchip Tool Flow for NoC Design -- Designing Standard Topologies -- Designing Custom Topologies -- Supporting Multiple Applications -- Supporting Dynamic Application Patterns -- NoC Reliability Mechanisms -- Timing-Error Tolerant NoC Design -- Analysis of NoC Error Recovery Schemes -- Fault-Tolerant Route Generation -- NoC Support for Reliable On-Chip Memories -- Conclusions and Future Directions.