On and Off-Chip Crosstalk Avoidance in VLSI Design
On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus t...
Κύριοι συγγραφείς: | , , |
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Συγγραφή απο Οργανισμό/Αρχή: | |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2010.
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- On-Chip Crosstalk and Avoidance
- of On-Chip Crosstalk Avoidance
- Preliminaries to On-chip Crosstalk
- Memoryless Crosstalk Avoidance Codes
- CODEC Designs for Memoryless Crosstalk Avoidance Codes
- Memory-based Crosstalk Avoidance Codes
- Multi-valued Logic Crosstalk Avoidance Codes
- Summary of On-Chip Crosstalk Avoidance
- Off-Chip Crosstalk and Avoidance
- to Off-Chip Crosstalk
- Package Construction and Electrical Modeling
- Preliminaries and Terminology
- Analytical Model for Off-Chip Bus Performance
- Optimal Bus Sizing
- Bus Expansion Encoder
- Bus Stuttering Encoder
- Impedance Compensation
- Future Trends and Applications
- Summary of Off-Chip Crosstalk Avoidance.