The Power of Assertions in SystemVerilog

• Κύριοι συγγραφείς: Cerny, Eduard (Συγγραφέας), Dudani, Surrendra (Συγγραφέας), Havlicek, John (Συγγραφέας), Korchemny, Dmitry (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Boston, MA : Springer US : Imprint: Springer, 2010.
• Έκδοση: First.
• Θέματα: Engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Electrical Engineering.

 The Power of Assertions in SystemVerilog is a comprehensive book that enables the reader to reap the full benefits of assertion-based verification in the quest to abate hardware verification cost. The book is divided into three parts. The first part introduces assertions, SystemVerilog and its simulation semantics. The second part delves into the details of assertions and their semantics. All property operators, in conjunction with ease-of-use features and examples, are discussed to illustrate the immense expressive power of the language. The third part presents an extended description of checkers and a methodology for building reusable checker libraries. The book concludes by outlining some desirable future enhancements. Detailed descriptions of the language features are provided throughout the book, along with their uses and how they play together to construct powerful sets of property checkers. The exposition of the features is supplemented with examples that take the reader step-by-step, from intuitive comprehension to much greater depth of understanding, enabling the reader to become an expert user. A unique aspect of the book is that it is oriented toward both simulation and formal verification. The semantics is discussed in terms of both simulation events and formal definition. This blended approach imparts profound conceptual and practical guidance for a broader spectrum of readers. The Power of Assertions in SystemVerilog is a valuable reference for design engineers, verification engineers, tool builders and educators. 

 Opening -- SystemVerilog Language and Simulation Semantics Overview -- Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Let Sequence and Property Declarations Inference -- Advanced Properties -- Advanced Sequences -- to Assertion Based Formal Verification -- Formal Verification and Models -- Clocks -- Resets -- Procedural Concurrent Assertions -- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Formal Semantics -- Checkers and Assertion Libraries -- Checkers -- Checkers in Formal Verification -- Checker Libraries -- Future Enhancements.