On-Chip Interconnect with aelite Composable and Predictable Systems /

• Κύριοι συγγραφείς: Hansson, Andreas (Συγγραφέας), Goossens, Kees (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: New York, NY : Springer New York : Imprint: Springer, 2011.
• Σειρά: Embedded Systems,
• Θέματα: Engineering.; Computer-aided engineering.; Electronic circuits.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.

 On-Chip Interconnect with aelite: Composable and Predictable Systems by: (Authors) Andreas Hansson Kees Goossens Embedded systems are comprised of components integrated on a single circuit, a System on Chip (SoC). One of the critical elements of such an SoC, and the focus of this work, is the on-chip interconnect that enables different components to communicate with each other. The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs. •Uses real-world illustrations extensively, in the form of case studies and examples that communicate the power of the methods presented; •Uses one consistent, running example throughout the book. This example is introduced in the introductory chapter and supports the presentation throughout the work, with additional details given in each chapter; •Content has both breadth (architecture, resource allocation, hardware/software instantiation, formal verification) and depth (block-level architecture description, allocation algorithms, complete run-time APIs, detailed formal models, complete case studies mapped to FPGAs); •Includes numerous case studies, e.g. a JPEG decoder, set-top box and digital radio design.