Low-Power Variation-Tolerant Design in Nanometer Silicon

Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-thresh...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Bhunia, Swarup (Editor), Mukhopadhyay, Saibal (Editor)
Format: Electronic eBook
Language:English
Published: Boston, MA : Springer US, 2011.
Edition:1.
Subjects:
Online Access:Full Text via HEAL-Link
Table of Contents:
  • Introduction and Motivation
  • Background on Power Dissipation
  • Background on Parameter Variations
  • Low power Logic Design under Variations
  • Low Power Memory Design under Variations
  • System and Architecture Level Design
  • Emerging Challenges and Solution Approach
  • Conclusion and Discussion.