Application-Specific Mesh-based Heterogeneous FPGA Architectures

Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However,...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς: Parvez, Husain (Συγγραφέας), Mehrez, Habib (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: New York, NY : Springer New York, 2011.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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020 |a 9781441979285  |9 978-1-4419-7928-5 
024 7 |a 10.1007/978-1-4419-7928-5  |2 doi 
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100 1 |a Parvez, Husain.  |e author. 
245 1 0 |a Application-Specific Mesh-based Heterogeneous FPGA Architectures  |h [electronic resource] /  |c by Husain Parvez, Habib Mehrez. 
264 1 |a New York, NY :  |b Springer New York,  |c 2011. 
300 |a XVII, 150 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
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505 0 |a Introduction -- State of the Art -- FPGA Layout Generation -- ASIF: Application Specific Inflexible FPGA -- ASIF using Heterogeneous Logic Blocks -- ASIF Hardware Generation -- Conclusion and Future Lines of Research. 
520 |a Low volume production of FPGA-based products is quite effective and economical because they are easy to design and program in the shortest amount of time. The generic reconfigurable resources in an FPGA can be programmed to execute a wide variety of applications at mutually exclusive times. However, the flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs. Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures.  It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required.  Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures. Presents a new exploration environment for mesh-based, heterogeneous FPGA architectures; Describes state-of-the-art techniques for reducing area requirements in FPGA architectures; Enables reduction in power required and increase in performance. 
650 0 |a Engineering. 
650 0 |a Electronics. 
650 0 |a Microelectronics. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
700 1 |a Mehrez, Habib.  |e author. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781441979278 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4419-7928-5  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)