Error Control for Network-on-Chip Links
As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed t...
| Κύριοι συγγραφείς: | , |
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| Συγγραφή απο Οργανισμό/Αρχή: | |
| Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
| Γλώσσα: | English |
| Έκδοση: |
New York, NY :
Springer New York,
2012.
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| Έκδοση: | 1. |
| Θέματα: | |
| Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- Introduction
- Solutions to Improve the Reliability of On-Chip Interconnects
- Networks-on-Chip (NoC)
- Error Control Coding for On-Chip Interconnects
- Energy Efficient Error Control Implementation
- Combining Error Control Codes with Crosstalk Reduction.