Error Control for Network-on-Chip Links

As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed t...

Full description

Bibliographic Details
Main Authors: Fu, Bo (Author), Ampadu, Paul (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: New York, NY : Springer New York, 2012.
Edition:1.
Subjects:
Online Access:Full Text via HEAL-Link
Table of Contents:
  • Introduction
  • Solutions to Improve the Reliability of On-Chip Interconnects
  • Networks-on-Chip (NoC)
  • Error Control Coding for On-Chip Interconnects
  • Energy Efficient Error Control Implementation
  • Combining Error Control Codes with Crosstalk Reduction.