Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

• Κύριοι συγγραφείς: Ahuja, Sumit (Συγγραφέας), Lakshminarayana, Avinash (Συγγραφέας), Shukla, Sandeep Kumar (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: New York, NY : Springer New York, 2012.
• Θέματα: Engineering.; Computer-aided engineering.; Electronic circuits.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.

Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phon...

Πίνακας περιεχομένων:

• Introduction
• Related Work
• Background
• Architectural Selection using High Level Synthesis
• Statistical Regression Based Power Models
• Coprocessor Design Space Exploration Using High Level Synthesis
• Regression-based Dynamic Power Estimation for FPGAs
• High Level Simulation Directed RTL Power Estimation
• Applying Verification Collaterals for Accurate Power Estimation
• Power Reduction using High-Level Clock-gating
• Model-Checking to exploit Sequential Clock-gating
• System Level Simulation Guided Approach for Clock-gating
• Conclusions.