Transient and Permanent Error Control for Networks-on-Chip

This book addresses reliability and energy efficiency of on-chip networks using a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for...

Full description

Bibliographic Details
Main Authors: Yu, Qiaoyan (Author), Ampadu, Paul (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: New York, NY : Springer New York, 2012.
Subjects:
Online Access:Full Text via HEAL-Link
LEADER 03191nam a22004815i 4500
001 978-1-4614-0962-5
003 DE-He213
005 20151125221220.0
007 cr nn 008mamaa
008 111117s2012 xxu| s |||| 0|eng d
020 |a 9781461409625  |9 978-1-4614-0962-5 
024 7 |a 10.1007/978-1-4614-0962-5  |2 doi 
040 |d GrThAP 
050 4 |a TK7888.4 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
082 0 4 |a 621.3815  |2 23 
100 1 |a Yu, Qiaoyan.  |e author. 
245 1 0 |a Transient and Permanent Error Control for Networks-on-Chip  |h [electronic resource] /  |c by Qiaoyan Yu, Paul Ampadu. 
264 1 |a New York, NY :  |b Springer New York,  |c 2012. 
300 |a XII, 160 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Introduction -- Existing Transient and Permanent Error Management in NoCs -- Adaptive Error Control Coding at Datalink Layer -- Transient and Permanent Link Errors Co-Management -- Dual-Layer Cooperative Error Control for Transient Error -- A Flexible Parallel Simulator for Networks-on-Chip with Error Control -- Conclusions and Future Directions. . 
520 |a This book addresses reliability and energy efficiency of on-chip networks using a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for parity-check bits. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance. Includes a complete survey of error control methods for reliable networks-on-chip, evaluated for reliability, energy and performance metrics; Provides analysis of error control in various network-on-chip layers, as well as presentation of an innovative multi-layer error control coding technique; Presents state-of-the-art solutions to address simultaneously reliability, energy and performance; Describes configurable error management solutions and their hardware implementation details for variable noise conditions; Provides details of a flexible and parallel NoC simulator and corresponding simulation setup to achieve the reported results.    . 
650 0 |a Engineering. 
650 0 |a Nanotechnology. 
650 0 |a Electronics. 
650 0 |a Microelectronics. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
650 2 4 |a Nanotechnology and Microengineering. 
700 1 |a Ampadu, Paul.  |e author. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781461409618 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4614-0962-5  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)