Design for Manufacturability From 1D to 4D for 90–22 nm Technology Nodes /

This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes.  It is a valuable guide for layout designers, packaging engineers a...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Balasinski, Artur (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: New York, NY : Springer New York : Imprint: Springer, 2014.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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001 978-1-4614-1761-3
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007 cr nn 008mamaa
008 131005s2014 xxu| s |||| 0|eng d
020 |a 9781461417613  |9 978-1-4614-1761-3 
024 7 |a 10.1007/978-1-4614-1761-3  |2 doi 
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082 0 4 |a 621.3815  |2 23 
100 1 |a Balasinski, Artur.  |e author. 
245 1 0 |a Design for Manufacturability  |h [electronic resource] :  |b From 1D to 4D for 90–22 nm Technology Nodes /  |c by Artur Balasinski. 
264 1 |a New York, NY :  |b Springer New York :  |b Imprint: Springer,  |c 2014. 
300 |a VIII, 278 p. 214 illus., 45 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Preface -- Classic DfM: from 2D to 3D -- DfM at 28 nm and Beyond -- New DfM Domain: Stress Effects -- Conclusions and Future Work. 
520 |a This book explains integrated circuit design for manufacturability (DfM) at the product level (packaging, applications) and applies engineering DfM principles to the latest standards of product development at 22 nm technology nodes.  It is a valuable guide for layout designers, packaging engineers and quality engineers, covering DfM development from 1D to 4D, involving IC design flow setup, best practices, links to manufacturing and product definition, for process technologies down to 22 nm node, and product families including memories, logic, system-on-chip and system-in-package. ·         Provides design for manufacturability guidelines on layout techniques for the most advanced, 22 nm  technology nodes; ·         Includes information valuable to layout designers, packaging engineers and quality engineers, working on memories, logic, system-on-chip and system-in-package;  ·         Offers a highly-accessible, single-source reference to information otherwise available only from disparate sources; ·         Helps readers to translate reliability methodology into real design flows. 
650 0 |a Engineering. 
650 0 |a Quality control. 
650 0 |a Reliability. 
650 0 |a Industrial safety. 
650 0 |a Electronics. 
650 0 |a Microelectronics. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
650 2 4 |a Quality Control, Reliability, Safety and Risk. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781461417606 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4614-1761-3  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)