UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

• Κύριοι συγγραφείς: Daněk, Martin (Συγγραφέας), Kafka, Leoš (Συγγραφέας), Kohout, Lukáš (Συγγραφέας), Sýkora, Jaroslav (Συγγραφέας), Bartosinski, Roman (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: New York, NY : Springer New York : Imprint: Springer, 2013.
• Θέματα: Engineering.; Microprocessors.; Electronics.; Microelectronics.; Electronic circuits.; Circuits and Systems.; Processor Architectures.; Electronics and Microelectronics, Instrumentation.

 This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.  Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language.    . 

 Introduction -- The LEON3 Processor -- Microthreaded Extensions -- The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example -- UTLEON3 Implementation Details -- Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads -- I/O and Interrupt Handling in the Microthread Mode -- The IU3 Pipeline -- Excerpts from the LEON3 Instruction Set -- Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example -- Used Resources -- Tutorial.