Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) /

This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς: Gangadharan, Sridhar (Συγγραφέας), Churiwala, Sanjay (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: New York, NY : Springer New York : Imprint: Springer, 2013.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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100 1 |a Gangadharan, Sridhar.  |e author. 
245 1 0 |a Constraining Designs for Synthesis and Timing Analysis  |h [electronic resource] :  |b A Practical Guide to Synopsys Design Constraints (SDC) /  |c by Sridhar Gangadharan, Sanjay Churiwala. 
264 1 |a New York, NY :  |b Springer New York :  |b Imprint: Springer,  |c 2013. 
300 |a XXVII, 226 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
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505 0 |a Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinatorial Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC Commands -- XDC: Xilinx Extensions To SDC. 
520 |a This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.  ·         Provides a hands-on guide to synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints; ·         Includes key topics of interest to a synthesis, static timing analysis or  place and route engineer; ·         Explains which constraints command to use for ease of maintenance and reuse, given several options possible to achieve the same effect on timing; ·         Explains fundamental concepts and provides exact command syntax. 
650 0 |a Engineering. 
650 0 |a Microprocessors. 
650 0 |a Electronics. 
650 0 |a Microelectronics. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
650 2 4 |a Processor Architectures. 
700 1 |a Churiwala, Sanjay.  |e author. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781461432685 
856 4 0 |u http://dx.doi.org/10.1007/978-1-4614-3269-2  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)