Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) /

• Κύριοι συγγραφείς: Gangadharan, Sridhar (Συγγραφέας), Churiwala, Sanjay (Συγγραφέας)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: New York, NY : Springer New York : Imprint: Springer, 2013.
• Θέματα: Engineering.; Microprocessors.; Electronics.; Microelectronics.; Electronic circuits.; Circuits and Systems.; Electronics and Microelectronics, Instrumentation.; Processor Architectures.

This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis...

Πίνακας περιεχομένων:

• Introduction
• Synthesis Basics
• Timing Analysis and Constraints
• SDC Extensions through Tcl
• Clocks
• Generated Clocks
• Clock Groups
• Other Clock Characteristics
• Port Delays
• Completing Port Constraints
• False Paths
• Multi Cycle Paths
• Combinatorial Paths
• Modal Analysis
• Managing Your Constraints
• Miscellaneous SDC Commands
• XDC: Xilinx Extensions To SDC.