Pipelined Multiprocessor System-on-Chip for Multimedia

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs).  A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς: Javaid, Haris (Συγγραφέας), Parameswaran, Sri (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2014.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
LEADER 03407nam a22004815i 4500
001 978-3-319-01113-4
003 DE-He213
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020 |a 9783319011134  |9 978-3-319-01113-4 
024 7 |a 10.1007/978-3-319-01113-4  |2 doi 
040 |d GrThAP 
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072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
082 0 4 |a 621.3815  |2 23 
100 1 |a Javaid, Haris.  |e author. 
245 1 0 |a Pipelined Multiprocessor System-on-Chip for Multimedia  |h [electronic resource] /  |c by Haris Javaid, Sri Parameswaran. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2014. 
300 |a VIII, 169 p. 40 illus., 32 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Introduction -- Literature Survey -- Optimisation Framework -- Performance Estimation of Pipelined MPSoCs -- Design Space Exploration of Pipelined MPSoCs -- Adaptive Pipelined MPSoCs -- Power Management in Adaptive Pipelined MPSocs -- Multi-mode Pipelined MPSoCs -- Conclusions and Future Work. 
520 |a This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs).  A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint.  A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.   ·         Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCs; ·         Includes analytical models and estimation methods for performance estimation of pipelined MPSoCs; ·         Covers several design space exploration techniques for pipelined MPSoCs; ·         Introduces an adaptive pipelined MPSoC with run-time processor and power managers; ·         Introduces Multi-mode pipelined MPSoCs for multiple applications.    . 
650 0 |a Engineering. 
650 0 |a Microprocessors. 
650 0 |a Electronics. 
650 0 |a Microelectronics. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Processor Architectures. 
650 2 4 |a Electronics and Microelectronics, Instrumentation. 
700 1 |a Parameswaran, Sri.  |e author. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9783319011127 
856 4 0 |u http://dx.doi.org/10.1007/978-3-319-01113-4  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)