Broadband Direct RF Digitization Receivers

This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level a...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Jamin, Olivier (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2014.
Σειρά:Analog Circuits and Signal Processing, 121
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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100 1 |a Jamin, Olivier.  |e author. 
245 1 0 |a Broadband Direct RF Digitization Receivers  |h [electronic resource] /  |c by Olivier Jamin. 
264 1 |a Cham :  |b Springer International Publishing :  |b Imprint: Springer,  |c 2014. 
300 |a XVI, 162 p. 166 illus., 68 illus. in color.  |b online resource. 
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490 1 |a Analog Circuits and Signal Processing,  |x 1872-082X ;  |v 121 
505 0 |a RF Receiver Architecture State-of-the-Art -- System-Level Design Framework for Direct RF Digitization Receivers -- Application to the System Design of a Multi-Channel Cable Receiver -- Realization & Measurements -- Conclusions & Perspectives. 
520 |a This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis.  Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.  ·         Provides system-level analysis of direct RF sampling & digitization receivers, from the antenna to the digital channel selection; ·         Includes analysis of broadband non-linearity, applicable for low-pass and band-pass sampling strategies; Describes system-level design of an application-optimized signal conditioner, including a single-inductance multi-slope programmable RF amplitude equalizer, together with its control algorithm and a mixed-signal AGC loop combining RMS and peak detection.  . 
650 0 |a Engineering. 
650 0 |a Microprocessors. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Signal, Image and Speech Processing. 
650 2 4 |a Processor Architectures. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9783319011493 
830 0 |a Analog Circuits and Signal Processing,  |x 1872-082X ;  |v 121 
856 4 0 |u http://dx.doi.org/10.1007/978-3-319-01150-9  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)