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03662nam a22004695i 4500 |
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978-3-319-01150-9 |
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DE-He213 |
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20151031081046.0 |
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130906s2014 gw | s |||| 0|eng d |
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|a 9783319011509
|9 978-3-319-01150-9
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|a 10.1007/978-3-319-01150-9
|2 doi
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|a TEC008010
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|a 621.3815
|2 23
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|a Jamin, Olivier.
|e author.
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|a Broadband Direct RF Digitization Receivers
|h [electronic resource] /
|c by Olivier Jamin.
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|a Cham :
|b Springer International Publishing :
|b Imprint: Springer,
|c 2014.
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300 |
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|a XVI, 162 p. 166 illus., 68 illus. in color.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
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|a text file
|b PDF
|2 rda
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|a Analog Circuits and Signal Processing,
|x 1872-082X ;
|v 121
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|a RF Receiver Architecture State-of-the-Art -- System-Level Design Framework for Direct RF Digitization Receivers -- Application to the System Design of a Multi-Channel Cable Receiver -- Realization & Measurements -- Conclusions & Perspectives.
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|a This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains. A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis. Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption. · Provides system-level analysis of direct RF sampling & digitization receivers, from the antenna to the digital channel selection; · Includes analysis of broadband non-linearity, applicable for low-pass and band-pass sampling strategies; Describes system-level design of an application-optimized signal conditioner, including a single-inductance multi-slope programmable RF amplitude equalizer, together with its control algorithm and a mixed-signal AGC loop combining RMS and peak detection. .
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|a Engineering.
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|a Microprocessors.
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|a Electronic circuits.
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|a Engineering.
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|a Circuits and Systems.
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|a Signal, Image and Speech Processing.
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|a Processor Architectures.
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|a SpringerLink (Online service)
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|t Springer eBooks
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|i Printed edition:
|z 9783319011493
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830 |
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|a Analog Circuits and Signal Processing,
|x 1872-082X ;
|v 121
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856 |
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|u http://dx.doi.org/10.1007/978-3-319-01150-9
|z Full Text via HEAL-Link
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|a ZDB-2-ENG
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|a Engineering (Springer-11647)
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