Flip-Flop Design in Nanometer CMOS From High Speed to Low Energy /

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit desig...

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Bibliographic Details
Main Authors: Alioto, Massimo (Author), Consoli, Elio (Author), Palumbo, Gaetano (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Cham : Springer International Publishing : Imprint: Springer, 2015.
Subjects:
Online Access:Full Text via HEAL-Link
Table of Contents:
  • The Logical Effort Method
  • Design in the Energy-Delay Space
  • Clocked Storage Elements
  • Flip-Flop Optimized Design
  • Analysis and Comparison in the Energy-Delay-Area Domain
  • Energy Efficiency Versus Clock Slope
  • Hold Time Issues and Impact of variations on Flip-Flop Topologies
  • Ultra-Fast and Energy-Efficient Pulsed Latch Topologies.