Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge res...
| Main Authors: | Noia, Brandon (Author), Chakrabarty, Krishnendu (Author) |
|---|---|
| Corporate Author: | SpringerLink (Online service) |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
|
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
Similar Items
-
Testing of Interposer-Based 2.5D Integrated Circuits
by: Wang, Ran, et al.
Published: (2017) -
Trace-Based Post-Silicon Validation for VLSI Circuits
by: Liu, Xiao, et al.
Published: (2014) -
3D Stacked Chips From Emerging Processes to Heterogeneous Systems /
Published: (2016) -
The Boundary-Scan Handbook
by: Parker, Kenneth P.
Published: (2016) -
Exploring Memory Hierarchy Design with Emerging Memory Technologies
by: Sun, Guangyu
Published: (2014)