Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

• Main Authors: Noia, Brandon (Author), Chakrabarty, Krishnendu (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Cham : Springer International Publishing : Imprint: Springer, 2014.
• Subjects: Engineering.; Microprocessors.; Semiconductors.; Electronic circuits.; Circuits and Systems.; Processor Architectures.

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge res...

Table of Contents:

• Introduction
• Wafer Stacking and 3D Memory Test
• Built-in Self-Test for TSVs
• Pre-Bond TSV Test Through TSV Probing
• Pre-Bond TSV Test Through TSV Probing
• Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths
• Post-Bond Test Wrappers and Emerging Test Standards
• Test-Architecture Optimization and Test Scheduling
• Conclusions.